M16C80 Datasheet, PDF (149/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
17. Clock synchronous serial I/O mode
Table 17.2 Specifications of clock synchronous serial I/O mode (2)
Item
Error detection
Select function
Specification
• Overrun error (Note 1)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note 2)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
_______ _______
• Separate CTS/RTS pins (UART0) (Note 2)
_______
_______
UART0 CTS and RTS pins each can be assigned to separate pins
• Switching serial data logic (UART2 to UART4)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2 to UART4)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Note 1: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit will not change.
_______ _______
Note 2: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
Rev.1.00 Aug. 02, 2005 ^{Page 138} of 329
REJ09B0187-0100