M16C80 Datasheet, PDF (272/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
Memory expansion Mode and Microprocessor Mode (with 3 wait)
Read Timing
BCLK
ALE
CSi
25ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
25ns.max*1
tcyc
th(BCLK-CS)
0ns.min
th(RD-CS)
0ns.min
td(BCLK2-5AnDs.)max*1
ADi
BHE
td(BCLK-RD)
10ns.max
RD
tac2(RD-DB)*2
tac2(AD-DB)*2
th(BCLK-AD)
0ns.min
th(RD-AD)
0ns.min
th(BCLK-RD)
-3ns.min
DB
Hi-Z
tsu(DB-BCLK)
40ns.min*1
th(RD-DB)
0ns.min
*1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).
*2:It depends on operation frequency.
tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
ALE
CSi
ADi
BHE
WR,WRL,
WRH
DBi
25ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
25ns.max
tcyc
td(BCLK-AD)
25ns.max
td(BCLK-WR) _tw(WR)*3
25ns.max
td(DB-WR)*3
th(BCLK-CS)
0ns.min
th(WR-CS)*3
th(BCLK-AD)
0ns.min
th(WR-AD)*3
th(BCLK-WR)
0ns.min
th(WR-DB)*3
Vcc=3V
*3:It depends on operation frequency.
td(DB-WR)=(tcyc x n-40)ns.min
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
th(WR-DB)=(tcyc/2-20)ns.min
th(WR-AD)=(tcyc/2-20)ns.min
th(WR-CS)=(tcyc/2-20)ns.min
tw(WR)=(tcyc/2 x n-20)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 28.18 VCC=3V timing diagram (4)
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Rev.1.00 Aug. 02, 2005 ^{Page 261} of 329
REJ09B0187-0100