M16C80 Datasheet, PDF (348/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
Revision History
Version
Contents for change
Page 204 Making power consumption electricity small --> addition
Page 207 Table 1.28.3 VT+ – VT- SCL2-SCL4, SDA2-SDA4 Addition
Page 208 Table 1.28.5 Note Change
Page 215 Table 1.28.22 tRP expression change
Page 217-220 Figure 1.28.2-1.28.5
tw(WR) addition, th(BCLK-DB) delate
Page 219, 220, 222, 223, 225
Figure 1.28.4, 1.28.5, 1.28.7, 1.28.8, 1.28.10 addition
Page 225, 226 Figure 1.28.10, 1.28.11 th(BCLK-DB) -5 ns.min --> -7 ns.min
Page 227 Figure 1.28.12 Refresh timing (self refresh) RAS timing
Page 230 3V of electric characteristics addition
Page 246 Table 1.29.1 Data hold --> addition
Page 247 Figure 1.29.2 Package type 144P6Q --> 144P6Q-A
Page 248 Flash memory line 5 change
Page 250 Function outline Line 24 (Parallel ... function ) --> delate
Page 269 Standard serial I/O mode Line 26 externl device --> external device ( programmer)
Page 285 Figure1.31.21 programer --> peripheral unit ( programmer)
Rev.D3
Page 43 Figure1.8.4 Note of the system clock control register 0-->addition
Page 44 Line 4 Note-->addition
Page 45 Table1.8.2 Note-->addition
Page 71 Line 9 "Address match interrupt is not generated with a start instruction of interrupt
routine."-->Delete
Page 73 (6) Precaution of Address mach interrupt-->addition
Page 79 Figure1.11.2 Note-->change
Page 87 Precaution for DMAC-->addition
Page 131 Figure1.16.11 Bit 7-->Must set to "1" in selecting IIC mode.
Page 152 Figure1.20.1 Bit 7-->Must set to "1" in selecting IIC mode.
Page 182 Addition
Page 205 (3) Address match interrupt in Interrupt precautions-->addition
Page 206 (2) DMAC-->addition
Page 207 Precautions for using CLKOUT pin-->addition
Page 210 Table1.28.3 Icc when clock stop Topr=25C^o-->change
Page 212 Table1.28.6 External clock input HIGH and LOW pulse waidth 22-->20
External clock rise and fall time 10-->5
Page 215, 216 Table1.28.19, 20 th(BCLK-DB)-->delete, tw(WR)-->addition
Page 218 Table1.28.22 th(BCLK-DB) -5ns --> -7ns
Page 233 Table1.28.23 Icc when clock stop Topr=25C^o-->change
Page 235 Table1.28.27 th(CAS-DB)-->addition
Page 238, 239 Table1.28.39, 40 tw(WR) -->addition, th(BCLK-RD) 0ns-->-3ns
Page 240 Table1.28.41 td(AD-ALE)=10⁹/(f(BCLK)X2)-20 -->10⁹/(f(BCLK)X2)-27
Page 241 Table1.28.42 th(BCLK-CAS) 0ns-->-3ns
Page 242 Figure1.28.15 tac1(RD-DB) min-->max, tac1(AD-DB) min-->max
Page 243 Figure1.28.16 tac2(RD-DB) min-->max, tac2(AD-DB) min-->max
Page 244, 255 Figure1.28.17 2 wait, Figure1.28.18 3 wait-->addition
Page 246 Figure1.28.19 tac3(AD-DB)-->addition, tsu(DB-RD)-->tsu(DB-BCLK), th(BCLK-RD) 0ns -->-
3ns, td(AD-ALE)=(tcyc/2-20)ns--> ... -27)ns
Page 247 Figure1.28.20 Addition
Page 248, 249 Figure1.28.21, 1.28.22 -->addition
Revision
date
19/6/'00
C-8