M16C80 Datasheet, PDF (199/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
25. DRAM Controller
< Read cycle (wait control bit = 1) >
BCLK
MA0 to MA12
Row
Column _{Column Column}
address address 1 address 2 address 3
RAS
CASH
CASL
'H'
DW
Column
address 4
D0 to D15
(EDO mode)
Note : Only CASL is operating in 8-bit data bus width.
< Write cycle (wait control bit = 1) >
BCLK
MA0 to MA12
Row
Column Column Column
address address 1 address 2 address 3
Column
address 4
RAS
CASH
CASL
DW
D0 to D15
Note : Only CASL is operating in 8-bit data bus width.
Figure 25.5 The bus timing during DRAM access (2)
Rev.1.00 Aug. 02, 2005 ^{Page 188} of 329
REJ09B0187-0100