M16C80 Datasheet, PDF (43/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
7. Bus
Table 7.3 Each processor mode and port function
Processor Single-chip
mode
mode
Memory expansion mode/microprocessor modes
Memory
expansion mode
Multiplexed
bus space
select bit
“01”, “10”
CS1 or CS2 : multiplexed
bus, and the other :
separate bus
“00”
Separate bus
“11” (Note 1)
All space multiplexed
bus
Data bus width
BYTE pin level
P00 to P07 I/O port
All external
area is 8 bits
Data bus
Some external All external
area is 16 bits area is 8 bits
Data bus
Data bus
Some external
area is 16 bits
Data bus
All external _{Some external}
area is 8 bits _{area is 16 bits}
I/O port
I/O port
P10 to P17 I/O port I/O port
Data bus
I/O port
Data bus
I/O port
I/O port
P20 to P27
P30 to P37
P40 to P43
I/O port
I/O port
I/O port
Address bus
/data bus
(Note 2)
Address bus
Address bus
Address bus
/data bus
(Note 2)
Address bus
/data bus
(Note 2)
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus Address bus
/data bus
/data bus
Address bus Address bus
/data bus
I/O port
I/O port
P44 to P46
P47
P50 to P53
P54
I/O port
I/O port
I/O port
I/O port
CS (chip select) or address bus (A20 to A22)
(For details, refer to “Bus control”) (Note 5)
CS (chip select) or address bus (A23)
(For details, refer to “Bus control”) (Note 5)
Outputs RD, WRL, WRH and BCLK, or RD, BHE, WR and BCLK
(For details, refer to “Bus control”) (Note 3,4)
HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3)
P55
I/O port HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
P56
I/O port RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3)
P57
I/O port RDY
RDY
RDY
RDY
RDY
RDY
Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in
microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Note 2: Address bus in separate bus configuration.
Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1.
Note 4: When you have selected use of the DRAM controller and you access the DRAM area, these are CASL, CASH, DW, and
BCLK outputs.
Note 5: The CS signal and address bus selection are set by the external area mode.
Rev.1.00 Aug. 02, 2005 ^{Page 32} of 329
REJ09B0187-0100