M16C80 Datasheet, PDF (262/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25^oC unless otherwise specified)
Table 28.24 External clock input
Symbol
Parameter
tc
tw(H)
tw(L)
tr
tf
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Standard
Unit
Min. Max.
100
ns
40
ns
40
ns
18
ns
18
ns
Table 28.25 Memory expansion and microprocessor modes
Symbol
tac1(RD-DB)
tac1(AD-DB)
tac2(RD-DB)
tac2(AD-DB)
tac3(RD-DB)
tac3(AD-DB)
tac4(RAS-DB)
tac4(CAS-DB)
tac4(CAD-DB)
tsu(DB-BCLK)
tsu(RDY-BCLK )
tsu(HOLD-BCLK )
th(RD-DB)
th(CAS-DB)
th(BCLK -RDY)
th(BCLK-HOLD )
td(BCLK-HLDA )
Parameter
Data input access time (RD standard, no wait)
Data input access time (AD standard, CS standard, no wait)
Data input access time (RD standard, with wait)
Data input access time (AD standard, CS standard, with wait)
Data input access time (RD standard, when accessing multiplex bus area)
Data input access time (AD standard, CS standard, when accessing
multiplex bus area)
Data input access time (RAS standard, DRAM access)
Data input access time (CAS standard, DRAM access)
Data input access time (CAD standard, DRAM access)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
Standard
Min. Max.
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
40
60
80
0
0
0
0
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
10 ⁹
tac1(RD – DB) = _{f(BCLK) X 2} – 42 [ns]
tac1(AD – DB) =
10 ⁹
f(BCLK)
– 55 [ns]
10 ⁹X m
tac2(RD – DB) = _{f(BCLK) X 2}
– 42
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
tac2(AD – DB) =
10⁹ X n
f(BCLK)
– 55 _{[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)}
tac3(RD – DB) =
10⁹ X m
f(BCLK) X 2
– 55
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
tac3(AD – DB) =
10⁹ X n
f(BCLK) X 2
– 55
[ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
tac4(RAS – DB) =
10 ⁹X m
f(BCLK) X 2
– 55
[ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
tac4(CAS – DB) =
10⁹ X n _{– 55}
f(BCLK) X 2
[ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
tac4(CAD – DB) =
10 ⁹X l
f(BCLK)
– 55 [ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
Rev.1.00 Aug. 02, 2005 ^{Page 251} of 329
REJ09B0187-0100