M16C80 Datasheet, PDF (144/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
16. Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
When reset
036516,036D16
0216
Bit
symbol
Bit name
TE
Transmit enable bit
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
0 : Transmission disabled 0 : Transmission disabled
1 : Transmission enabled 1 : Transmission enabled
TI
Transmit buffer
empty flag
RE Receive enable bit
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag 0 : No data present in
0 : No data present in
receive buffer register
receive buffer register
1 : Data present in
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
When write, set "0". When read, the value of these bits is “0”.
RW
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1 (i=2 to 4)
Address
When reset
033D16, 032D16, 02FD16
0216
Bit
symbol
Bit name
TE Transmit enable bit
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
0 : Transmission disabled 0 : Transmission disabled
1 : Transmission enabled 1 : Transmission enabled
TI Transmit buffer
empty flag
RE Receive enable bit
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
RI Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
UiIRS
UARTi transmit interrupt
cause select bit
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
UiRRM UARTi continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Set to “0”
UiLCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
UiERE Error signal output
enable bit
Set to “0”
0 : Output disabled
1 : Output enabled
RW
Figure 16.9 Serial I/O-related registers (5)
Rev.1.00 Aug. 02, 2005 ^{Page 133} of 329
REJ09B0187-0100