M16C80 Datasheet, PDF (196/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
25. DRAM Controller
• Refresh
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The refresh method is CAS before RAS. The refresh interval is set by the DRAM refresh interval set
register (address 004116). The refresh signal is not output in HOLD state. Figure 25.3 shows the DRAM
refresh interval set register.
Use the following formula to determine the value to set in the refresh interval set register.
Refresh interval set register value (0 to 255) = refresh interval time / (BCLK frequency X 32) - 1
DRAM refresh interval set register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
REFCNT
Address
0004116
When reset
Indeterminate
Bit symbol
Bit name
REFCNT0 Refresh interval set bit
REFCNT1
REFCNT2
Function
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 : 1.6 µs
0 0 0 0 0 0 0 1 : 3.2 µs
0 0 0 0 0 0 1 0 : 4.8 µs
RW
REFCNT3
•
REFCNT4
•
•
REFCNT5
REFCNT6
1 1 1 1 1 1 1 1 : 409.6 µs
REFCNT7
(Note)
Note: Refresh interval at 20 MHz operating (no division)
Refresh interval = BCLK frequency X (refresh interval set bit + 1) X 32
Figure 25.3 DRAM refresh interval set register
Rev.1.00 Aug. 02, 2005 ^{Page 185} of 329
REJ09B0187-0100