M16C80 Datasheet, PDF (78/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time that
consists of 24* cycles.
Time (b) is shown in Table 9.6.
* It is when the divisor is immediate or register. When the divisor is memory, the following value is
added.
• Normal addressing
:2+X
• Index addressing
:3+X
• Indirect addressing
: 5 + X + 2Y
• Indirect index addressing : 6 + X + 2Y
X is number of wait of the divisor area. Y is number of wait of the indirect address stored area.
When X and Y are in odd address or in 8 bits bus area, double the value of X and Y.
Table 9.6 Interrupt Sequence Execution Time
Interrupt
Interrupt vector address 16 bits data bus 8 bits data bus
Peripheral I/O
INT instruction
_______
NMI
Watchdog timer
Undefined instruction
Address match
Overflow
BRK instruction (Variable vector table)
Single step
BRK2 instruction
BRK instruction (Fixed vector table)
High-speed interrupt (Note 3)
Even address
Odd address (Note 1)
Even address
Odd address (Note 1)
Even address (Note 2)
Even address (Note 2)
Even address
Odd address (Note 1)
Even address (Note 2)
Vector table is internal
register
14 cycles
16 cycles
12 cycles
14 cycles
13 cycles
16 cycles
16 cycles
14 cycles
14 cycles
15 cycles
14 cycles
17 cycles
19 cycles
19 cycles
16 cycles
19 cycles
19 cycles
21 cycles
5 cycles
Note 1: Allocate interrupt vector addresses in even addresses, if possible.
Note 2: The vector table is fixed to even address.
Note 3: The high-speed interrupt is independent of these conditions.
Rev.1.00 Aug. 02, 2005 ^{Page 67} of 329
REJ09B0187-0100