M16C80 Datasheet, PDF (61/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
8. Clock Generating Circuit
8.5 Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. Table 8.5 shows the status of the ports in
wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts using as BCLK the clock that had been selected when the WAIT instruction was
executed.
When using an interrupt to exit Wait mode, the relevant interrupt must have been enabled and set to a
priority level above the level set by the interrupt priority set bits for exiting a stop/wait state (bits 2, 1, and 0
at address 009F16). Set the interrupt priority set bits for the exit from a stop/wait state to the same level as
the flag register (FLG) processor interrupt level (IPL).
The priority level of the interrupt which is not used to cancel wait mode, must have been changed to 0.
When using an interrupt to exit Wait mode, the microcomputer resumes operating the clock that was oper-
ating when the WAIT command was executed as BCLK from the interrupt routine.
______
If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all
interrupt to 0, then shift to wait mode.
Table 8.5 Port status during wait mode
Pin
Memory expansion mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3,
________
BHE
_____ ______ ________ _________ ______ _________
RD, WR, WRL, WRH, DW, CASL,
________
CASH
________
RAS
__________
HLDA,BCLK
Microprocessor mode
Retains status before wait mode
“H” (Note)
“H” (Note)
“H”
ALE
“L”
Port
Retains status before wait mode Retains status before wait mode
CLKOUT
When fC selected Does not stop
When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit
is “0”. When the WAIT peripheral function clock stop bit is “1”,
the status immediately prior to entering wait mode is main-
tained.
________
________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.
Rev.1.00 Aug. 02, 2005 ^{Page 50} of 329
REJ09B0187-0100