MC68HC08AZ60A Datasheet, PDF (53/480 Pages) Motorola, Inc – Microcontrollers

Memory Map
Vector Addresses and Priority
Table 2-1. Vector addresses (Continued)⁽¹⁾
Highest Priority
Address
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Vector
SPI Transmit Vector (High)
SPI Transmit Vector (Low)
SPI Receive Vector (High)
SPI Receive Vector (Low)
TIMB Overflow Vector (High)
TIMB Overflow Vector (Low)
TIMB CH1 Vector (High)
TIMB CH1 Vector (Low)
TIMB CH0 Vector (High)
TIMB CH0 Vector (Low)
TIMA Overflow Vector (High)
TIMA Overflow Vector (Low)
TIMA CH3 Vector (High)
TIMA CH3 Vector (Low)
TIMA CH2 Vector (High)
TIMA CH2 Vector (Low)
TIMA CH1 Vector (High)
TIMA CH1 Vector (Low)
TIMA CH0 Vector (High)
TIMA CH0 Vector (Low)
PIT Vector (High)
PIT Vector (Low)
PLL Vector (High)
PLL Vector (Low)
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
1. All available ROM locations not defined by the user will by
default be filled with the software interrupt (SWI, opcode 83)
instruction – see Central Processor Unit (CPU). Take this into
account when defining vector addresses. It is recommended that
ALL vector addresses are defined.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Memory Map
Advance Information
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