MC68HC08AZ60A Datasheet, PDF (124/480 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
8.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
• A POR pulse is generated
• The internal reset signal is asserted
• The SIM enables CGMOUT
• Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow the oscillator to stabilize
• The RST pin is driven low during the oscillator stabilization time
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared
OSC1
PORRST
CGMXCLK
CGMOUT
RST
IAB
Advance Information
124
4096
CYCLES
32
CYCLES
32
CYCLES
Figure 8-6. POR Recovery
$FFFE
$FFFF
System Integration Module (SIM)
MC68HC08AZ60A — Rev 0.0
MOTOROLA