MC68HC08AZ60A Datasheet, PDF (267/480 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
Queuing Transmission Data
WRITE TO SPDR ¹
3
8
SPTE
2
5
10
SCK (CPHA:CPOL =‘1’:0)
MOSI
SPRF
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
654321
654321
654
BYTE 1
BYTE 2
BYTE 3
4
9
READ SPSCR
6
11
READ SPDR
7
12
1 CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
2 BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
3 CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.
7 CPU READS SPDR, CLEARING SPRF BIT.
8 CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
Figure 17-10. SPRF/SPTE CPU Interrupt Timing
For a slave, the transmit data buffer allows back-to-back transmissions
to occur without the slave having to time the write of its data between the
transmissions. Also, if no new data is written to the data buffer, the last
value contained in the shift register will be the next data word
transmitted.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Serial Peripheral Interface (SPI)
Advance Information
267