MC68HC08AZ60A Datasheet, PDF (277/480 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
I/O Registers
The SPI status and control register also contains bits that perform the
following functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Bit 7
6
5
4
3
2
1
SPSCR
Read: SPRF
Write:
ERRIE
OVRF
MODF
SPTE
MODFE
N
SPR1
Reset: 0
0
0
0
1
0
0
R = Reserved
= Unimplemented
Figure 17-13. SPI Status and Control Register (SPSCR)
Bit 0
SPR0
0
SPRF — SPI Receiver Full
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Any read of the SPI data register clears the SPRF
bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable
This read-only bit enables the MODF and OVRF flags to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Flag
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next byte enters the shift
register. In an overflow condition, the byte already in the receive data
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Serial Peripheral Interface (SPI)
Advance Information
277