MC68HC08AZ60A Datasheet, PDF (170/480 Pages) Motorola, Inc – Microcontrollers

Mask Options
Bit 7
6
5
4
3
2
1
Bit 0
MORB
$FE09
Read: EEDIVCLK
Write:
R
R
EEMONSEC AZ60A
R
R
R
Reset:
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 10-2. Mask Option Register B (MORB)
EEDIVCLK — EEPROM-1 and EEPROM-2 Timebase Dividers Clock
Select Bit
EEDIVCLK selects the reference clock source for the EEPROM-1 and
EEPROM-2 timebase dividers. See EEPROM-1 Timebase Divider
Register on page 74 and EEPROM-2 Timebase Divider Register
on page 94.
1 = CPU bus clock drives the EEPROM-1 and EEPROM-2
timebase dividers
0 = CGMXCLK drives the EEPROM-1 and EEPROM-2 timebase
dividers
EEMONSEC — EEPROM Read Protection in Monitor Mode Bit
When EEMONSEC is set, the entire EEPROM-1 and EEPROM-2
arrays cannot be acessed in monitor mode unless a valid security
code is entered.
1 = EEPROM-1 and EEPROM-2 read protection in monitor mode
enabled.
0 = EEPROM-1 and EEPROM-2 read protection in monitor mode
disabled.
AZ60A — Device Indicator (Not user-selectable)
This bit is set to a logic ’1’.
Extra care should be exercised when selecting mask option
registers since other HC08 family parts may have different options.
If in doubt, check with your local field applications representative.
Advance Information
170
Mask Options
MC68HC08AZ60A — Rev 0.0
MOTOROLA