MC68HC08AZ60A Datasheet, PDF (308/480 Pages) Motorola, Inc – Microcontrollers

Programmable Interrupt Timer (PIT)
modulo value programmed in the PIT counter modulo registers. The PIT
interrupt enable bit, POIE, enables PIT overflow CPU interrupt requests.
POF and POIE are in the PIT status and control register.
19.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
19.6.1 Wait Mode
The PIT remains active after the execution of a WAIT instruction. In wait
mode the PIT registers are not accessible by the CPU. Any enabled CPU
interrupt request from the PIT can bring the MCU out of wait mode.
If PIT functions are not required during wait mode, reduce power
consumption by stopping the PIT before executing the WAIT instruction.
19.6.2 Stop Mode
The PIT is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the PIT
counter. PIT operation resumes when the MCU exits stop mode after an
external interrupt.
19.7 PIT During Break Interrupts
A break interrupt stops the PIT counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see SIM Break Flag Control Register
(SBFCR) on page 137).
Advance Information
308
Programmable Interrupt Timer (PIT)
MC68HC08AZ60A — Rev 0.0
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