MC68HC08AZ60A Datasheet, PDF (270/480 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
To protect status bits during the break state, a ‘0’ should be written to the
BCFE bit. With BCFE at ‘0’ (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is a ‘0’. After the break, the
second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission, nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
17.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel
I/O port.
• MISO — data received
• MOSI — data transmitted
• SPSCK — serial clock
• SS — slave select
• V_SS — clock ground
The SPI has limited inter-integrated circuit (I²C) capability (requiring
software support) as a master in a single-master environment. To
communicate with I²C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I²C
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I²C peripheral and through a pullup resistor to
V_DD.
Advance Information
270
Serial Peripheral Interface (SPI)
MC68HC08AZ60A — Rev 0.0
MOTOROLA