MC68HC08AZ60A Datasheet, PDF (119/480 Pages) Motorola, Inc – Microcontrollers

STOP/WAIT
CONTROL
SIM
COUNTER
÷2
CLOCK
CONTROL
CLOCK GENERATORS
System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 8-1. SIM Block Diagram
Table 8-1. SIM I/O Register Summary
Register Name
Bit 7 6
R:
SIM Break Status Register (SBSR)
R
R
W:
R: POR PIN
SIM Reset Status Register (SRSR)
W:
SIM Break Flag Control Register
(SBFCR)
BCFE R
5
4
3
R
R
R
COP ILOP ILAD
R
R
R
R = Reserved for factory test
2
1 Bit 0 Addr.
BW
R
R $FE00
0
0
LVI 0
$FE01
R
R
R $FE03
= Unimplemented
MC68HC08AZ60A — Rev 0.0
MOTOROLA
System Integration Module (SIM)
Advance Information
119