MC68HC08AZ60A Datasheet, PDF (196/480 Pages) Motorola, Inc – Microcontrollers

Low Voltage Inhibit (LVI)
14.3 Features
Features of the LVI module include the following:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of VDD pin level
NOTE:
If a low voltage interrupt (LVI) occurs during programming of EEPROM
memory, then adequate programming time may not have been allowed
to ensure the integrity and retention of the data. It is the responsibility of
the user to ensure that in the event of an LVI any addresses being
programmed receive specification programming conditions.
14.4 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V_DD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V_DD falls below a voltage, LVI_TRIPF, and remains at or below
that level for 9 or more consecutive CPU cycles.
Note that short V_DD spikes may not trip the LVI. It is the user’s
responsibility to ensure a clean V_DD signal within the specified
operating voltage range if normal microcontroller operation is to be
guaranteed.
LVISTOP enables the LVI module during stop mode. This will ensure
when the STOP instruction is implemented the LVI will continue to
monitor the voltage level on V_DD.
LVIPWR, LVIRST and LVISTOP are mask options. See Mask Options
on page 167. Once an LVI reset occurs, the MCU remains in reset until
V_DD rises above a voltage, LVI_TRIPR. V_DD must be above LVI_TRIPR for only
one CPU cycle to bring the MCU out of reset. The output of the
comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
Advance Information
196
Low Voltage Inhibit (LVI)
MC68HC08AZ60A — Rev 0.0
MOTOROLA