MC68HC08AZ60A Datasheet, PDF (123/480 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Reset and System Initialization
8.4.2 Active Resets From Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow for resetting of external peripherals. The internal reset
signal IRST continues to be asserted for an additional 32 cycles. See
Figure 8-4. An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. See Figure 8-5. Note that for LVI or
POR resets, the SIM cycles through 4096 CGMXCLK cycles, during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST as shown in Figure
8-4.
IRST
RST
CGMXCLK
IAB
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
VECTOR HIGH
Figure 8-4. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 8-5. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
System Integration Module (SIM)
Advance Information
123