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MC68HC08AZ60A Datasheet, PDF (457/480 Pages) Motorola, Inc – Microcontrollers
Electrical Specifications
CGM Acquisition/Lock Time Information
25.11 CGM Acquisition/Lock Time Information
Description
Symbol
Min
Typ
Max Unit
Notes
Manual Mode Time to Stable tACQ
—
(8 x VDDA) /
(fCGMXCLK x KACQ)
—
s If CF Chosen
Correctly
Manual Stable to Lock Time
tAL
—
(4 x VDDA) /
(fCGMXCLK x KTRK)
—
s If CF Chosen
Correctly
Manual Acquisition Time
tLOCK
—
tACQ+tAL
—
s
Tracking Mode Entry
Frequency Tolerance
DTRK
0
—
± 3.6
%
Acquisition Mode Entry
Frequency Tolerance
DUNT
± 6.3
—
± 7.2
%
LOCK Entry Freq. Tolerance DLOCK
0
—
± 0.9
%
LOCK Exit Freq. Tolerance
DUNL
± 0.9
—
± 1.8
%
Reference Cycles per
Acquisition Mode
Measurement
nACQ
—
32
—
—
Reference Cycles per
Tracking Mode
Measurement
nTRK
—
128
—
—
Automatic Mode Time
to Stable
tACQ
nACQ/fCGM
XCLK
(8 x VDDA) /
(fCGMXCLK x KACQ)
s If CF Chosen
Correctly
Automatic Stable to Lock
Time
tAL
nTRK/fCGM
XCLK
(4 x VDDA) /
(fCGMXCLK x KTRK)
—
s If CF Chosen
Correctly
Automatic Lock Time
tLOCK
—
0.65
25
ms
PLL Jitter, Deviation of
Average Bus Frequency
over 2 ms (note 1)
0
—
± (fCRYS)
x (.025%)
%
N = VCO
Freq. Mult.
x (N/4)
K value for automatic mode
time to stable
Kacq
—
0.2
—
—
K value
Ktrk
—
0.004
—
—
NOTES:
1. Guaranteed but not tested.
2. VDD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, TA = -40C to TA (MAX), unless otherwise noted.
3. Conditions for typical and maximum values are for Run mode with fCGMXCLK = 8MHz, fBUSDES = 8MHz, N = 4, L = 7,
discharged CF = 15 nF, VDD = 5Vdc.
4. Refer to Phase-Locked Loop (PLL) section for guidance on the use of the PLL.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Electrical Specifications
Advance Information
457