MC68HC08AZ60A Datasheet, PDF (112/480 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Continued)
Source
Form
Operation
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M
LDHX #opr
LDHX opr
Load H:X from M
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
Load X from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Left
(Same as ASL)
Logical Shift Right
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP
NSA
Unsigned multiply
Negate (Two’s Complement)
No Operation
Nibble Swap A
Description
A ← (M)
H:X ← (M:M + 1)
X ← (M)
C
b7
0
b0
0
b7
C
b0
(M)_Destination ← (M)_Source
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
None
A ← (A[3:0]:A[7:4])
Effect on
CCR
VHI NZ C
IMM
DIR
EXT
0
–
–
↕
↕
–
IX2
IX1
IX
SP1
SP2
0
–
–
↕
↕
–
IMM
DIR
IMM
DIR
EXT
0
–
–
↕
↕
–
IX2
IX1
IX
SP1
SP2
DIR
INH
↕
–
–
↕
↕
↕
INH
IX1
IX
SP1
DIR
INH
↕
–
–
0
↕
↕
INH
IX1
IX
SP1
DD
0
–
–
↕
↕
–
DIX+
IMD
IX+D
– 0 – – – 0 INH
DIR
INH
↕
–
–
↕
↕
↕
INH
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
A6
B6
C6
D6
E6
F6
9E
ii
dd
hh
ll
ee
ff
ff
2
3
4
4
3
2
E6
9E
D6
ff
ee
ff
4
5
45 ii jj 3
55 dd 4
AE
BE
CE
DE
EE
FE
9E
ii
dd
hh
ll
ee
ff
ff
2
3
4
4
3
2
EE
9E
DE
ff
ee
ff
4
5
38
48
dd
58
68
78
ff
9E
68
ff
4
1
1
4
3
5
34
44
dd
54
64
74
ff
9E
64
ff
4
1
1
4
3
5
dd
4E dd 5
5E dd 4
6E ii
4
7E dd 4
dd
42
5
30
40
dd
50
60
70
ff
9E
60
ff
4
1
1
4
3
5
9D
1
62
3
Advance Information
112
Central Processor Unit (CPU)
MC68HC08AZ60A — Rev 0.0
MOTOROLA