MC68HC08AZ60A Datasheet, PDF (103/480 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
CPU registers
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
PC
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 7-5. Program Counter (PC)
7.4.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to ‘1’. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
CCR
V
1
1
H
I
N
Z
C
Write:
Reset: X
1
1
X
1
X
X
X
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Central Processor Unit (CPU)
Advance Information
103