MC68HC08AZ60A Datasheet, PDF (295/480 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module B (TIMB)
I/O Registers
18.9.1 TIMB Status and Control Register
The TIMB status and control register:
• Enables TIMB overflow interrupts
• Flags TIMB overflows
• Stops the TIMB counter
• Resets the TIMB counter
• Prescales the TIMB counter clock
Address: $0040
Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
R
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
R = Reserved
Figure 18-4. TIMB Status and Control Register (TBSC)
TOF — TIMB Overflow Flag Bit
This read/write flag is set when the TIMB counter reaches the modulo
value programmed in the TIMB counter modulo registers. Clear TOF
by reading the TIMB status and control register when TOF is set and
then writing a logic 0 to TOF. If another TIMB overflow occurs before
the clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.
1 = TIMB counter has reached modulo value
0 = TIMB counter has not reached modulo value
TOIE — TIMB Overflow Interrupt Enable Bit
This read/write bit enables TIMB overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Timer Interface Module B (TIMB)
Advance Information
295