MC68HC08AZ60A Datasheet, PDF (143/480 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Functional Description
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLLIE
PLLON BCS
PLL Control Register (PCTL) Write:
Reset: 0
0
1
0
1
1
1
1
Read:
LOCK
0
0
0
0
PLL Bandwidth Control Register
(PBWC)
Write:
AUTO
ACQ
XLD
Reset: 0
0
0
0
0
0
0
0
Read:
PLL Programming Register (PPG) Write:
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
= Unimplemented
Figure 9-2. I/O Register Summary
Table 9-1. I/O Register Address Summary
Register
Address
PCTL
$001C
PBWC
$001D
PPG
$001E
9.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
9.4.2.1 Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Clock Generator Module (CGM)
Advance Information
143