MC68HC08AZ60A Datasheet, PDF (155/480 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
CGM Registers
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See 9.4.3 on page 149.
PCTL3–PCTL0 — Unimplemented
These bits provide no function and always read as logic 1s.
9.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register:
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOCK
0
0
0
0
AUTO
ACQ
XLD
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-5. PLL Bandwidth Control Register (PBWC)
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Clock Generator Module (CGM)
Advance Information
155