MC68HC08AZ60A Datasheet, PDF (316/480 Pages) Motorola, Inc – Microcontrollers

I/O Ports
20.2 Introduction
Fifty bidirectional input-output (I/O) pins form eight parallel ports. All I/O
pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Table 20-1. I/O Port Register Summary
Register Name
Bit 7
6
5
4
3
2
1 Bit 0 Addr.
Port A Data Register (PTA)
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 $0000
Port B Data Register (PTB)
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001
Port C Data Register (PTC) ^R:
W:
Port D Data Register (PTD)
0
PTD7
0
PTD6
PTC5
PTD5
PTC4
PTD4
PTC3
PTD3
PTC2
PTD2
PTC1
PTD1
PTC0 $0002
PTD0 $0003
Data Direction Register A (DDRA)
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004
Data Direction Register B (DDRB)
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005
Data Direction Register C (DDRC) ^R: MCLKEN ⁰ DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 $0006
W:
Data Direction Register D (DDRD) DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 $0007
Port E Data Register (PTE)
PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 $0008
Port F Data Register (PTF) ^{R: 0}
W:
PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 $0009
Port G Data Register (PTG) ^{R: 0}
W:
0
0
0
0
PTG2 PTG1 PTG0 $000A
Port H Data Register (PTH) ^{R: 0}
W:
0
0
0
0
0
PTH1 PTH0 $000B
Data Direction Register E (DDRE)
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 $000C
Data Direction Register F (DDRF) ^{R: 0} DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 $000D
W:
Advance Information
316
I/O Ports
MC68HC08AZ60A — Rev 0.0
MOTOROLA