MC68HC08AZ60A Datasheet, PDF (310/480 Pages) Motorola, Inc – Microcontrollers

Programmable Interrupt Timer (PIT)
Address: $004B
Bit 7
6
5
4
3
2
1
Bit 0
Read: POF
0
0
POIE PSTOP
PPS2 PPS1 PPS0
Write: 0
PRST
Reset: 0
0
1
0
0
0
0
0
= Unimplemented
Figure 19-3. PIT Status and Control Register (PSC)
POF — PIT Overflow Flag Bit
This read/write flag is set when the PIT counter reaches the modulo
value programmed in the PIT counter modulo registers. Clear POF by
reading the PIT status and control register when POF is set and then
writing a logic 0 to POF. If another PIT overflow occurs before the
clearing sequence is complete, then writing logic 0 to POF has no
effect. Therefore, a POF interrupt request cannot be lost due to
inadvertent clearing of POF. Reset clears the POF bit. Writing a logic
1 to POF has no effect.
1 = PIT counter has reached modulo value
0 = PIT counter has not reached modulo value
POIE — PIT Overflow Interrupt Enable Bit
This read/write bit enables PIT overflow interrupts when the POF bit
becomes set. Reset clears the POIE bit.
1 = PIT overflow interrupts enabled
0 = PIT overflow interrupts disabled
PSTOP — PIT Stop Bit
This read/write bit stops the PIT counter. Counting resumes when
PSTOP is cleared. Reset sets the PSTOP bit, stopping the PIT
counter until software clears the PSTOP bit.
1 = PIT counter stopped
0 = PIT counter active
Advance Information
310
Programmable Interrupt Timer (PIT)
MC68HC08AZ60A — Rev 0.0
MOTOROLA