MC68HC08AZ60A Datasheet, PDF (198/480 Pages) Motorola, Inc – Microcontrollers

Low Voltage Inhibit (LVI)
LVIRST bits must be at ‘1’ to enable the LVI module and to enable LVI
resets.
14.4.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,V_DD must
remain at or below the LVI_TRIPF level for 9 or more consecutive CPU
cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the
MCU out of reset.
14.5 LVI Status Register (LVISR)
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Bit 7
6
5
4
3
2
1
Bit 0
LVISR ^{Read: LVIOUT}
0
0
0
0
0
0
0
$FE0F _Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when V_DD falls below the LVI_TRIPF
voltage for 32-40 CGMXCLK cycles. (See Table 14-2). Reset clears
the LVIOUT bit.
Advance Information
198
Low Voltage Inhibit (LVI)
MC68HC08AZ60A — Rev 0.0
MOTOROLA