MC68HC08AZ60A Datasheet, PDF (338/480 Pages) Motorola, Inc – Microcontrollers

I/O Ports
20.9.2 Data Direction Register G (DDRG)
Data direction register G determines whether each port G pin is an input
or an output. Writing a logic one to a DDRG bit enables the output buffer
for the corresponding port G pin; a logic zero disables the output buffer.
DDRG
$000E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
DDRG2 DDRG1 DDRG0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-20. Data Direction Register G (DDRG)
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE: Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 20-21 shows the port G I/O logic.
Advance Information
338
READ DDRG ($000E)
WRITE DDRG ($000E)
RESET
WRITE PTG ($000A)
READ PTG ($000A)
DDRGx
PTGx
PTGx
Figure 20-21. Port G I/O Circuit
I/O Ports
MC68HC08AZ60A — Rev 0.0
MOTOROLA