MC68HC08AZ60A Datasheet, PDF (200/480 Pages) Motorola, Inc – Microcontrollers

Low Voltage Inhibit (LVI)
14.7.2 Stop Mode
With LVISTOP=1 and LVIPWR=1 in the MORA register, the LVI module
will be active after a STOP instruction. Because CPU clocks are disabled
during stop mode, the LVI trip must bypass the digital filter to generate a
reset and bring the MCU out of stop.
With the LVIPWR bit in the MORA register at a logic 1 and the LVISTOP
bit at a logic 0, the LVI module will be inactive after a STOP instruction.
Advance Information
200
Low Voltage Inhibit (LVI)
MC68HC08AZ60A — Rev 0.0
MOTOROLA