MC68HC08AZ60A Datasheet, PDF (203/480 Pages) Motorola, Inc – Microcontrollers

External Interrupt Module (IRQ)
Functional Description
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to ‘1’
The vector fetch or software clear may occur before or after the interrupt
pin returns to ‘1’. As long as the pin is low, the interrupt request remains
pending. A reset will clear the latch and the MODE control bit, thereby
clearing the interrupt even if the pin stays low.
Table 15-1. IRQ I/O Register Summary
Register Name
Bit 7 6
5
4
3
2
Read: 0
0
0
0
IRQF
0
IRQ Status/Control Register (ISCR)
Write: R
R
R
R
R
ACK
1 Bit 0 Addr.
IMASK MODE $001A
R = Reserved
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. See Figure 15-
2.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
External Interrupt Module (IRQ)
Advance Information
203