MC68HC08AZ60A Datasheet, PDF (297/480 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module B (TIMB)
I/O Registers
18.9.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE:
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL
by reading TBCNTL before exiting the break interrupt. Otherwise,
TBCNTL retains the value latched during the break.
Register Name and Address TBCNTH — $0041
Bit 7
6
5
4
3
2
1
Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
Write: R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
Bit 0
BIT 8
R
0
Register Name and Address TBCNTL — $0042
Bit 7
6
5
4
3
2
1
Bit 0
Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R R = Reserved
Figure 18-5. TIMB Counter Registers (TBCNTH and TBCNTL)
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Timer Interface Module B (TIMB)
Advance Information
297