MC68HC08AZ60A Datasheet, PDF (357/480 Pages) Motorola, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
Interrupts
Example 1: to receive the message IDs
xxxx xxxx x011 111x xxxx xxxx xxxx xxxx
IDMR1 etc. must be 111x xxx1, i.e. ID20,19,18,15 must be masked.
Example 2: to receive the message IDs
xxxx 0111 1111 111x xxxx xxxx xxxx xxxx
IDMR1 etc. must be 1xxx xxx1, i.e. ID20 and ID15 must be masked.
In general, using IDMR1 etc. 1111 xxx1, i.e. masking
ID20,19,18,SRR,15, hides the problem.
21.7 Interrupts
The MSCAN08 supports four interrupt vectors mapped onto eleven
different interrupt sources, any of which can be individually masked (for
details see MSCAN08 Receiver Flag Register (CRFLG) on page 383,
to MSCAN08 Transmitter Control Register on page 388).
• Transmit Interrupt: At least one of the three transmit buffers is
empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXE flags of the empty message buffers are
set.
• Receive Interrupt: A message has been received successfully and
loaded into the foreground receive buffer. This interrupt will be
emitted immediately after receiving the EOF symbol. The RXF flag
is set.
• Wakeup Interrupt: An activity on the CAN bus occurred during
MSCAN08 internal sleep mode or power-down mode (provided
SLPAK = WUPIE = 1).
• Error Interrupt: An overrun, error, or warning condition occurred.
The receiver flag register (CRFLG) will indicate one of the
following conditions:
– Overrun: An overrun condition as described in Receive
Structures on page 348, has occurred.
– Receiver Warning: The receive error counter has reached the
CPU Warning limit of 96.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
MSCAN08 Controller (MSCAN08)
Advance Information
357