MC68HC08AZ60A Datasheet, PDF (165/480 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
In manual mode, it is usually necessary to wait considerably longer than
t_Lock before selecting the PLL clock (see Base Clock Selector Circuit
on page 149), because the factors described in Parametric Influences
on Reaction Time on page 162, may slow the lock time considerably.
When defining a limit in software for the maximum lock time, the value
must allow for variation due to all of the factors mentioned in this section,
especially due to the C_F capacitor and application specific influences.
The calculated lock time is only an indication and it is the customer’s
responsibility to allow enough of a guard band for their application. Prior
to finalizing any software and while determining the maximum lock time,
take into account all device to device differences. Typically, applications
set the maximum lock time as an order of magnitude higher than the
measured value. This is considered sufficient for all such device to
device variation.
Motorola recommends measuring the lock time of the application system
by utilizing dedicated software, running in FLASH, EEPROM or RAM.
This should toggle a port pin when the PLL is first configured and
switched on, then again when it goes from acquisition to lock mode and
finally again when the PLL lock bit is set. The resultant waveform can be
captured on an oscilloscope and used to determine the typical lock time
for the microcontroller and the associated external application circuit.
e.g.
t_LOCK
t_ACQ
t_AL
Init. low
Signal on port pin
t_TRKComplete and Lock Set
t_ACQComplete
PLL Configured and switched on
NOTE: The filter capacitor should be fully discharged prior to making any
measurements.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Clock Generator Module (CGM)
Advance Information
165