MC68HC08AZ60A Datasheet, PDF (106/480 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
7.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low--power
consumption standby modes.
7.6.1 WAIT Mode
The WAIT instruction:
• clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from WAIT mode by interrupt, the I
bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
7.6.2 STOP Mode
The STOP instruction:
• clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from STOP mode by
external interrupt, the I bit remains clear. After exit by reset, the I
bit is set.
• Disables the CPU clock
After exiting STOP mode, the CPU clock begins running after the
oscillator stabilization delay.
7.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See Break Module. The program counter
vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).
A return from interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
Advance Information
106
Central Processor Unit (CPU)
MC68HC08AZ60A — Rev 0.0
MOTOROLA