MC68HC08AZ60A Datasheet, PDF (255/480 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
Functional Description
SPRF set and then reading the SPI data register. Writing to the SPI data
register clears the SPTIE bit.
MASTER MCU
SHIFT REGISTER
BAUD RATE
GENERATOR
MISO
MOSI
SPSCK
SS
SLAVE MCU
MISO
MOSI
SPSCK
SHIFT REGISTER
SS
V_DD
Figure 17-3. Full-duplex Master-Slave Connections
17.5.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave
mode the SPSCK pin is the input for the serial clock from the master
MCU. Before a data transmission occurs, the SS pin of the slave MCU
must be at logic ‘0’. SS must remain low until the transmission is
complete. See Mode Fault Error.
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it transfers to the receive data register, and the
SPRF bit is set. To prevent an overflow condition, slave software must
then read the SPI data register before another byte enters the shift
register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed (which is twice as fast as the fastest master
SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any
particular SPI baud rate. The baud rate only controls the speed of the
SPSCK generated by an SPI configured as a master. Therefore, the
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Serial Peripheral Interface (SPI)
Advance Information
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