MC68HC08AZ60A Datasheet, PDF (162/480 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See Manual and Automatic PLL
Bandwidth Modes on page 145).
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
9.10.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f_CGMRDV (please reference Figure 9-1 on
page 142). This frequency is the input to the phase detector and controls
how often the PLL makes corrections. For stability, the corrections must
be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the
reference the longer it takes to make these corrections. This parameter
is also under user control via the choice of crystal frequency f_CGMXCLK.
Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus a change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. See Choosing a Filter Capacitor on page 163.
Also important is the operating voltage potential applied to V_DDA. The
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Advance Information
162
Clock Generator Module (CGM)
MC68HC08AZ60A — Rev 0.0
MOTOROLA