MC68HC08AZ60A Datasheet, PDF (273/480 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
I/O Registers
regardless of the state of the data direction register of the shared I/O
port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register. See Table 17-
4.
Table 17-4. SPI Configuration
SPE SPMSTR MODFEN SPI CONFIGURATION
0
X
X
Not Enabled
1
0
X
Slave
1
1
0
Master without MODF
1
1
X = don’t care
1
Master with MODF
STATE OF SS LOGIC
General-purpose I/O; SS
ignored by SPI
Input-only to SPI
General-purpose I/O; SS
ignored by SPI
Input-only to SPI
17.12.5 V_SS
(Clock Ground)
V_SS is the ground return for the serial clock pin, SPSCK, and the ground
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the V_SS pin.
17.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Serial Peripheral Interface (SPI)
Advance Information
273