MC68HC08AZ60A Datasheet, PDF (324/480 Pages) Motorola, Inc – Microcontrollers

I/O Ports
20.5.2 Data Direction Register C (DDRC)
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic one to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic zero disables the output buffer.
Bit 7
6
5
4
3
2
1
Bit 0
DDRC
$0006
Read:
MCLKEN
Write:
0
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-8. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, DDRC2 has no effect. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[5:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Advance Information
324
I/O Ports
MC68HC08AZ60A — Rev 0.0
MOTOROLA