MC68HC08AZ60A Datasheet, PDF (127/480 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Exception Control
8.5.2 SIM Counter During STOP Mode Recovery
The SIM counter is also used for STOP mode recovery. The STOP
instruction clears the SIM counter. After an interrupt or reset, the SIM
senses the state of the short STOP recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic ‘1’, then the STOP recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from STOP mode. External crystal
applications should use the full STOP recovery time, that is, with SSREC
cleared.
8.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See STOP mode for
details). The SIM counter is free-running after all reset states, see
Active Resets From Internal Sources on page 123 for counter control
and internal reset recovery sequences.
8.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
8.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents onto the stack and sets the interrupt mask (I-bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
MC68HC08AZ60A — Rev 0.0
MOTOROLA
System Integration Module (SIM)
Advance Information
127