MC68HC08AZ60A Datasheet, PDF (202/480 Pages) Motorola, Inc – Microcontrollers

External Interrupt Module (IRQ)
15.4 Functional Description
A ‘0’ applied to any of the external interrupt pins can latch a CPU
interrupt request. Figure 15-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following occurs:
• Vector fetch — a vector fetch automatically generates an interrupt
acknowledge signal which clears the latch that caused the vector
fetch.
• Software clear — software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic ‘1’ to the ACK bit clears the
IRQ latch.
• Reset — a reset automatically clears the interrupt latch.
ACK
VECTOR
FETCH
DECODER
TO CPU FOR
BIL/BIH
INSTRUCTIONS
V_DD
IRQF
IRQ
D ^CLR Q
CK
SYNCHRO-
NIZER
IRQ
INTERRUPT
REQUEST
IRQ
LATCH
IMASK
MODE
HIGH
VOLTAGE
DETECT
Figure 15-1. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
The external interrupt pin is falling-edge-triggered and is software-
configurable to be both falling-edge and low-level-triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
Advance Information
202
External Interrupt Module (IRQ)
MC68HC08AZ60A — Rev 0.0
MOTOROLA