MC68HC08AZ60A Datasheet, PDF (291/480 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module B (TIMB)
Functional Description
4. In TIMB channel x status and control register (TBSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB–MSxA (see Table 18-2).
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level (see Table 18-2).
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIMB status control register (TBSC) clear the TIMB stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output (see TIMB Channel
Status and Control Registers on page 299).
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Timer Interface Module B (TIMB)
Advance Information
291