MC68HC08AZ60A Datasheet, PDF (174/480 Pages) Motorola, Inc – Microcontrollers

Break Module
11.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
11.4.3 TIM and PIT During Break Interrupts
A break interrupt stops the timer counter.
11.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_HI is present on the
RST pin.
11.5 Break Module Registers
Three registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
Advance Information
174
Break Module
MC68HC08AZ60A — Rev 0.0
MOTOROLA