MC68HC08AZ60A Datasheet, PDF (359/480 Pages) Motorola, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
Protocol Violation Protection
21.7.2 Interrupt Vectors
The MSCAN08 supports four interrupt vectors as shown in Table 21-1.
The vector addresses and the relative interrupt priority are defined in
Table 2-1.
Table 21-1. MSCAN08 Interrupt Vector Addresses
Function
Wakeup
Error
Interrupts
Receive
Transmit
Source
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
TXE0
TXE1
TXE2
Local
Mask
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
TXEIE0
TXEIE1
TXEIE2
Global
Mask
I Bit
21.8 Protocol Violation Protection
The MSCAN08 will protect the user from accidentally violating the CAN
protocol through programming errors. The protection logic implements
the following features:
• The receive and transmit error counters cannot be written or
otherwise manipulated.
• All registers which control the configuration of the MSCAN08 can
not be modified while the MSCAN08 is on-line. The SFTRES bit in
the MSCAN08 module control register (see MSCAN08 Module
Control Register 0 on page 377) serves as a lock to protect the
following registers:
– MSCAN08 module control register 1 (CMCR1)
– MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1)
– MSCAN08 identifier acceptance control register (CIDAC)
– MSCAN08 identifier acceptance registers (CIDAR0–3)
MC68HC08AZ60A — Rev 0.0
MOTOROLA
MSCAN08 Controller (MSCAN08)
Advance Information
359