MC68HC08AZ60A Datasheet, PDF (327/480 Pages) Motorola, Inc – Microcontrollers

I/O Ports
Port D
TACLK/TBCLK — Timer clock input
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA.
The PTD4/TBCLK pin is the external clock input for the TIMB.The
prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK or
PTD4/TBCLK as the TIM clock input (see TIMA Channel Status and
Control Registers on page 424 and TIMB Status and Control
Register on page 295). When not selected as the TIM clock,
PTD6/TAClk and PTD4/TBCLK are available for general purpose I/O.
While TACLK/TBCLK are selected, corresponding DDRD bits have
no effect.
20.6.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
Bit 7
6
5
4
3
2
1
Bit 0
DDRD
$0007
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 20-11. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 20-12 shows the port D I/O logic.
When bit DDRDx is a logic one, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic zero, reading address $0003
reads the voltage level on the pin. The data latch can always be written,
MC68HC08AZ60A — Rev 0.0
MOTOROLA
I/O Ports
Advance Information
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