MC68HC08AZ60A Datasheet, PDF (131/480 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Low-Power Modes
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
8.8 Low-Power Modes
Executing the STOP/WAIT instruction puts the MCU in a low-power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
8.8.1 WAIT Mode
In WAIT mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 8-10 shows the timing for WAIT mode entry.
A module that is active during WAIT mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
WAIT mode, the CPU clocks are inactive. Refer to the WAIT mode
subsection of each module to see if the module is active or inactive in
WAIT mode. Some modules can be programmed to be active in WAIT
mode.
WAIT mode can also be exited by a reset or break. A break interrupt
during WAIT mode sets the SIM break WAIT bit, BW, in the SIM break
status register (SBSR). If the COP disable bit, COPD, in the mask option
register is ‘0’, then the computer operating properly (COP) module is
enabled and remains active in WAIT mode.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
System Integration Module (SIM)
Advance Information
131