MC68HC08AZ60A Datasheet, PDF (180/480 Pages) Motorola, Inc – Microcontrollers

Monitor ROM (MON)
12.4.1 Entering monitor mode
Table 12-1 shows the pin conditions for entering monitor mode.
Table 12-1. Mode Selection
Mode
CGMOUT
Bus
Frequency
V_HI⁽¹⁾
1 0 1 1 Monitor
C-----G-----M----2-X----C----L---K--- _or C-----G-----M----2-V----C----L---K---
C-----G-----M--2---O----U-----T--
V_HI⁽¹⁾
1 0 1 0 Monitor
CGMXCLK
C-----G-----M--2---O----U-----T--
1. For V_HI, 5.0 Volt DC Electrical Characteristics on page 448, and Maximum Ratings on page 446.
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a ‘0’ and then a ‘1’ to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes
(see Security on page 186). After the security bytes, the MCU sends a
break signal (10 consecutive ‘0’s) to the host computer, indicating that it
is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V_HI (see
Electrical Specifications on page 445), is applied to either the IRQ pin
or the RST pin. See System Integration Module (SIM) on page 117 for
more information on modes of operation.
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Advance Information
180
Monitor ROM (MON)
MC68HC08AZ60A — Rev 0.0
MOTOROLA