MC68HC08AZ60A Datasheet, PDF (383/480 Pages) Motorola, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
Programmer’s Model of Control Registers
21.14.5 MSCAN08 Receiver Flag Register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can be cleared only
when the condition which caused the setting is valid no more. Writing a
0 has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset will clear the
register.
Address: $0504
Bit 7
6
5
4
3
2
1
Bit 0
Read:
WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 21-19. Receiver Flag Register (CRFLG)
WUPIF — Wakeup Interrupt Flag
If the MSCAN08 detects bus activity while in Sleep mode, it sets the
WUPIF flag. If not masked, a wake-up interrupt is pending while this
flag is set.
1 = MSCAN08 has detected activity on the bus and requested
wake-up.
0 = No wake-up interrupt has occurred.
RWRNIF — Receiver Warning Interrupt Flag
This flag is set when the MSCAN08 goes into warning status due to
the receive error counter (REC) exceeding 96 and neither one of the
Error Interrupt flags or the Bus-off Interrupt flag is set⁽¹⁾. If not
masked, an error interrupt is pending while this flag is set.
1 = MSCAN08 has gone into receiver warning status.
0 = No receiver warning status has been reached.
1. Condition to set the flag: RWRNIF = (96 ð REC) & RERRIF & TERRIF & BOFFIF
MC68HC08AZ60A — Rev 0.0
MOTOROLA
MSCAN08 Controller (MSCAN08)
Advance Information
383