MC68HC08AZ60A Datasheet, PDF (241/480 Pages) Motorola, Inc – Microcontrollers

Serial Communications Interface (SCI)
I/O Registers
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1
and SCDR in the flag-clearing sequence. Figure 16-15 shows the
normal flag-clearing sequence and an example of an overrun caused by
a delayed flag-clearing sequence. The delayed read of SCDR does not
clear the OR bit because OR was not set when SCS1 was read. Byte 2
caused the overrun and is lost. The next flag-clearing sequence reads
byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-clearing
routine can check the OR bit in a second read of SCS1 after reading the
data register.
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 3
BYTE 4
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 3
Figure 16-15. Flag Clearing Sequence
BYTE 4
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Serial Communications Interface (SCI)
Advance Information
241